Computer Systems: A Programmer's Perspective (Global Edition): The Y86-64 Instruction Set Architecture

The Instruction Set Architecture (ISA) serves as the fundamental contract between software and hardware. It defines the programmer-visible state and the specific operations the processor executes. The Y86-64 ISA is an educational subset of x86-64, simplifying complex CISC designs into a more manageable model while retaining register-intensive procedure linkage.

1. Programmer-Visible State

The state includes the Register File (RF) with 15 registers, Condition Codes (CC) for flow control, the Program Counter (PC), and a Status Code (Stat) indicating normal operation (AOK), halting (HLT), or errors (ADR/INS).

2. CISC vs. RISC Characteristics

While x86-64 is classic CISC, Y86-64 trends toward RISC with fixed-length encodings and a strict load/store architecture, where memory is only accessed via specific move instructions like rmmovq rA, D(rB).

TERMINAL bash — 80x24

> Ready. Click "Run" to execute.

QUESTION 1

Modify the sum function (Figure 4.6) to implement absSum using a conditional jump. Which approach is most architecturally sound for Y86-64?

Using jge to skip a subq instruction that negates the value.

Using a call to a separate absolute value function.

Using a memory-to-memory comparison.

Changing the status code to INS if the value is negative.

QUESTION 2

When implementing absSum with conditional move (cmovXX), how do we handle the sign inversion?

Subtract the value from zero in a temporary register, then cmovl the negative result back.

Use the iaddq instruction to flip the bits.

Y86-64 performs sign inversion automatically during mrmovq.

Conditional moves cannot be used for arithmetic logic.

QUESTION 3

What is the byte encoding for the sequence: irmovq $15, %rbx; rrmovq %rbx, %rcx? (Starting at 0x100)

0x100: 30 f3 0f 00 00 00 00 00 00 00; 0x10a: 20 31

0x100: 30 3f 0f 00; 0x104: 20 13

0x100: 60 31; 0x102: 30 f3

0x100: 70 00; 0x102: 20 31

QUESTION 4

Determine the HCL code for the control signal mem_write in a SEQ processor.

bool mem_write = icode in { IRMMOVQ, IPUSHQ, ICALL };

bool mem_write = icode in { IMRMOVQ, IPOPQ, IRET };

bool mem_write = (valE == valM);

bool mem_write = stat == AOK;

QUESTION 5

In the PIPE implementation, when should the signal E_bubble be set?

On mispredicted branches or load-use hazards.

Every time the PC is updated.

Only when the processor hits a HALT instruction.

When the Register File is being read.

Case Study: Architectural Optimization and Logic

Advanced Y86-64 Implementation Details

You are tasked with extending the Y86-64 design. Consider the introduction of the iaddq instruction and the performance limits of a pipelined system with $k$ stages and overhead $T_{overhead}$.

1. [Writing Task] Rewrite the Y86-64 sum function of Figure 4.6 to make use of the iaddq instruction. (Output: ~14 lines).

Solution:
Model Solution: sum: irmovq $0, %rax # 1: sum = 0 andq %rsi, %rsi # 2: set CC jmp test # 3: start test loop: mrmovq (%rdi), %rdx # 4: get *start addq %rdx, %rax # 5: sum += *start iaddq $8, %rdi # 6: start++ (Optimization!) iaddq $-1, %rsi # 7: count-- (Optimization!) test: jg loop # 8: if count > 0, loop ret # 9: return (Note: This removes the need for registers %r8 and %r9 previously used to store constants 8 and 1.)

2. Write HCL code for a circuit that selects the median of word inputs A, B, and C.

Solution:
word median = [ (A <= B && B <= C) || (C <= B && B <= A) : B; (B <= A && A <= C) || (C <= A && A <= B) : A; 1 : C; ];

3. As the number of pipeline stages $k$ goes to infinity, what happens to the throughput?

Solution:
Throughput = 1 / (T/k + T_overhead). As k approaches infinity, the term T/k vanishes, and the throughput approaches a limit of 1 / T_overhead. This demonstrates that pipeline overhead eventually becomes the bottleneck for processor speed.